A test bench should be created to thoroughly test the ALU. You will call that module

ALU$\_$tb$.$v $.$

$1.$ Your design should have module named ALU which you will write in Modelsim.

The module statement must look exactly like this:

module ALU $($input $[3$:$0]$ aluin$\_$a$,$ aluin$\_$b$,$ OPCODE, input Cin,

output reg $[3$:$0]$ alu$\_$out, output reg Cout, output OF$)$;

$//$ your code to implement this ALU goes here!

endmodule

$($hint : see lecture $5$ section $4$ and Resources$/$Demos Port definitions and

underlying code$)$

The top$-$level module name should be named ALU as shown.

$2.$ Inside this module you should instantiate a $4-$bit ripple adder which in turn

instantiates a $1-$bit full adders. Inputs to the $4-$bit adder can be chosen based on

OPCODES using a case statement.

$3.4-$bit subtraction can be implemented by taking the $2$s complement of

aluin$\_$b prior to presenting it as an input to the adder module.

$4.$ Boolean expressions may be used for logical operations

OPCODEs for the ALU: The VERILOG model you implement should be for a $4-$bit

arithmetic$/$logic unit $($ALU$)$ which has as inputs two $4-$bit vectors aluin$\_$a and

aluin$\_$b as well as a $1-$bit carry in$,$ Cin. The output is a $4-$bit vector alu$\_$out. The ALU

should operate on the inputs depending on the $4-$bit OPCODE in the following table: