Question: A Verilog module named Sample is declared as below: module Sample ( clock , reset, w , Q ) ; where input and output ports

A Verilog module named "Sample" is declared as below:
module Sample(clock, reset, w, Q);
where input and output ports are defined as:
input clock, reset, w;
localparam m=8;
output reg [m-1:0] Q;
Q[0] is the right most bit and Q[m-1] is the left-most bit in the configuration.
Input w provides the serial input to the circuit.
Which of the following correctly implements a left-shift register?
A Verilog module named "Sample" is declared as below: module Sample(clock,

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