Write a Verilog module named alu corresponding to

the diagram shown below. The module has a w$-$bit in$-$

put B$,$ a $2-$bit input op$,$ a clock input clk$,$ and a w$-$bit

registered output $A.$ The module declaration should

include a parameter named $w$ for the bus widths with

a default value of $16.$ The use of the signals $x$ and $y$

is optional but they must be declared if they're used.

Bits should be numbered in decreasing order. Follow

the course coding conventions. You may omit com$-$

ments.

op$[0]$

op$[1]$

op$[0]$

$longrightarro{w}^2$

clk