$($a$)$ Write and verify an HDL behavioral description of a four$-$bit register with parallel load and asynchronous clear.

$($b$)$ Write and verify the HDL structural description of the four$-$bit register with parallel load shown in Fig. $6\mathrm{.}2.$ Use a $21$ multiplexer for the flip$-$flop inputs. Include an asynchronous clear input.

$($c$)$ Verify both descriptions, using a testbench.