An 8-processor SMP configuration uses MESI protocol to maintain cache coherence. Under MESI protocol, which of the following is possible for a particular cache line x in the memory?

	1.	Two processors each has x in M state, and the other six processor has it in S state
	2.	Two processors each has x in E state, and the other six processor all has it in S state
	3.	Two processors each has x in I state, and the other six processors each has it in S state
	4.	One processor has it in E state, another processor has it in M state, and all the other six processors each has it in I state.
	5.	None of the above.