Consider a situation in which four processors in an SMP configuration, over time, require access to the same line of data from main memory. All processors have a cache and use the MESI protocol. Initially, all caches have an invaid copy of the line. The following figure depicts the consequence of a read of line x by processor P1. If this is the start of a sequence of accesses, draw the subsequent figures for the following sequence: a. P1 writes x (for clarity, please label the line in P1's cache x1). b. P2 reads x. C. P3 reads x. d. P4 writes x (for clarity, please label the line in P4's cache x2). e. P4 writes x (for clarity, please label the line in P4's cache x3 f, p4 reads x. Main memory Memory access Cache Cache Cache Cache Snoop Processor Processor Processor Processor Consider a situation in which four processors in an SMP configuration, over time, require access to the same line of data from main memory. All processors have a cache and use the MESI protocol. Initially, all caches have an invaid copy of the line. The following figure depicts the consequence of a read of line x by processor P1. If this is the start of a sequence of accesses, draw the subsequent figures for the following sequence: a. P1 writes x (for clarity, please label the line in P1's cache x1). b. P2 reads x. C. P3 reads x. d. P4 writes x (for clarity, please label the line in P4's cache x2). e. P4 writes x (for clarity, please label the line in P4's cache x3 f, p4 reads x. Main memory Memory access Cache Cache Cache Cache Snoop Processor Processor Processor Processor