Consider a situation in which two processors in an SMP configuration, over time, require access to the
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1. P2 reads x.
2. P1 writes to x (for clarity, label the line in P1's cache
3. P1 writes to x (label the line in P1's cache
4. P2 reads x.
Figure 17.22 MESI Example: Processor 1 Reads Line x
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Related Book For
Computer organization and architecture designing for performance
ISBN: 978-0136073734
8th edition
Authors: william stallings
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