Consider a situation in which two processors in an SMP configuration, over time, require access to the same line of data from main memory. Both processors have a cache and use the MESI protocol. Initially, both caches have an invalid copy of the line. Figure 17.22 depicts the consequence of a read of line x by Processor P1. If this is the start of a sequence of accesses, draw the subsequent figures for the following sequence:
1. P2 reads x.
2. P1 writes to x (for clarity, label the line in P1's cache
3. P1 writes to x (label the line in P1's cache
4. P2 reads x.

Figure 17.22 MESI Example: Processor 1 Reads Line x

Main memory Memory accesS Cache Cache Snoop Processor Processor