April $29$

Cache block size B can affect both miss rate and miss latency. Assuming a $1-$CPI machine with an average of $1\mathrm{.}35$ references $($both instruction and data$)$ per

instruction, help find the optimal block size given the following hit rates for various block sizes.

a$)$ What is the optimal block size for a miss latency of $20*$ b cycles?

b$)$ What is the optimal block size for a miss latency of $24+b$ cycles?

c$)$ For constant miss latency what is the optimal block size?

We will look at two processors with the same main memory access time of $70$ nanoseconds and same instruction memory accesses of $36\%.$ The following

table shows data for L$1$ caches attached to two processors, P$1$ and P$2.$

a$)$ Assuming that the L$1$ hit time determines the cycle time for P$1$ and P$2,$ what are their respective clock rates?

b$)$ What is the average memory access time for P$1$ and P$2?$

c$)$ Assuming a base CPI of $1\mathrm{.}0$ without any memory stalls what is the total CPI for P$1$ and P$2?$ New line which processor is faster?

Use the table from problem $2$ and we now add an L$2$ cache to P$1$ to presumably make up for its limited L$1$ cache capacity. Use the L$1$ cache capacities and

hit rates from the previous table when solving these problems. The L$2$ hit rate in and access times are listed in the table. The L$2$ cache is only being added to

P$1.$

a$)$ What is the AMAT for $P1$ with the addition of the L$2$ cache? Is the AMAT better or worse with the

L$2$ cache?

b$)$ Assuming the base CPI of $1\mathrm{.}0$ without any memory cells what is the total CPI for P$1$ with the addition of the L$2$ cache? What would the L$2$ hit rate need to be

in order for P$1$ with an L$2$ cache to be faster than P$1$ without an L$2$ cache?

c$)$ What would the L$2$ hit rate need to be in order for P$1$ with an L$2$ cache to be faster than P$2$ without an L$2$ cache?