As you know the Control unit takes the opcode as input and generates control signals as in the figure above.

Fill in the following truth table:

Add LI ALU Add result Shift left 2 Reg2Loc Uncondbranch Branch MemRead MemtoReg Instruction [31-21] Control ALU MemWrite ALUSrc RegWrite Instruction [9-5] Instruction [20-16register 1 Read Read Read address PC data 1 MRead xregister 2 LIl Zero ALU ALU result Instruction [31-0] Address Read data Read Write register data 2 Write data Registers Instruction Instruction [4-0 LuI memory Write Data data memory Instruction [31-0] 32Sign 64 ALU control extend Instruction [31-21] Add LI ALU Add result Shift left 2 Reg2Loc Uncondbranch Branch MemRead MemtoReg Instruction [31-21] Control ALU MemWrite ALUSrc RegWrite Instruction [9-5] Instruction [20-16register 1 Read Read Read address PC data 1 MRead xregister 2 LIl Zero ALU ALU result Instruction [31-0] Address Read data Read Write register data 2 Write data Registers Instruction Instruction [4-0 LuI memory Write Data data memory Instruction [31-0] 32Sign 64 ALU control extend Instruction [31-21]