Question: - ASSIGNMENT-2 Q1) Design a JK flip flop with behavioral level in verilog. Then simulate it with testbench module. (Take screen shots from your codes

- ASSIGNMENT-2 Q1) Design a JK flip flop with behavioral level

- ASSIGNMENT-2 Q1) Design a JK flip flop with behavioral level in verilog. Then simulate it with testbench module. (Take screen shots from your codes and simulation's output) CIK J K Q Q State 1 0 0 0 0 No change in state Clk C JK Flip Flop 1 0 1 0 1 Resets Q to 0 1 1 0 1 0 Sets Qto 1 1 1 1 Toggles K 0

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