Question: digital system design Q1) Design a JK flip flop with behavioral level in verilog. Then simulate it with testbench module. (Take screen shots from your

digital system design

Q1) Design a JK flip flop with behavioral level in verilog. Then simulate it with testbench module. (Take screen shots from your codes and simulation's output.) Q Clk C. - JK Flip Flop Cik J K Q Q State 10 0 0 0 No change in Q state 1 0101 Resets Q to 0 1 1 0 1 0 Sets Q to 1 1 1 1 Toggles K 1

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