Question: solve them please Q1) Design a Full Adder with gate level in verilog. Then simulate it with testbench module. (Take screen shots from your codes

solve them please

Q1) Design a Full Adder with gate level in verilog. Then simulate it with testbench module. (Take screen shots from your codes and simulation's output.) Q2) Design a 2x4 Decoder with gate level in verilog. Then simulate it with testbench module. (Take screen shots from your codes and simulation's output.) AD Y B Yo E

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