Assume a $4-$core system, each core $2-$way SMT$,$ where each core has a private L$1$ followed by a shared

bus to main memory. Assume that all ca

e lines $($blocks$)$ are initially invalid. Using the MSI protocol,

simulate the coherence state of cache lines FOO and BAR. Assume that threads $0$ and $1$ are mapped to

core $0,$ threads $2$ and $3$ are mapped to core $1,$ thread $4$ is mapped to Core $2,$ and thread $5$ is mapped to core

$3.$ Varia