Assume a 5-stage pipelined CPU (IF ID - MU- EX WR) requires following time...

 

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Assume a 5-stage pipelined CPU (IF – ID - MU- EX – WR) requires following time for different sections: Pipeline stages Fetch Unit Required time 15 ns Decode Unit 10 ns Memory Unit Execution Unit 20 ns 8 ns 15 ns Write back Unit The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. b) Show the time steps and calculate the execution time for above problem while a multiport RAM is used with the system. Assume a 5-stage pipelined CPU (IF – ID - MU- EX – WR) requires following time for different sections: Pipeline stages Fetch Unit Required time 15 ns Decode Unit 10 ns Memory Unit Execution Unit 20 ns 8 ns 15 ns Write back Unit The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. b) Show the time steps and calculate the execution time for above problem while a multiport RAM is used with the system.