Assume a direct-mapped, write-through cache that maps 512 and 1024 to the same block, and a four-word write buffer that is not checked on a read miss. Will the value in R2 always be equal to the value in R3?

Problem #4: Look at this code sequence: SW R3, 512 (RO) LW R1, 1024 (RO) LW R2, 512 (RO) ;M[512) :R1 : R2 + R3 (cache index 0) + M[1024] (cache index 0) + M[512] (cache index 0) Assume a direct-mapped, write-through cache that maps 512 and 1024 to the same block, and a four- word write buffer that is not checked on a read miss. Will the value in R2 always be equal to the value in R3