$($a$)$ Given a direct$-$mapped write$-$through cache with $32-$bit memory addresses, tag bits

are bit $12$ to bit $31$ in the memory address, the cache block index bits are bit $5$ to bit $11,$

and the offset bits are bit $0$ to bit $4$:

$$ What is the line size $($i$.$e$.,$ block size$)$ in bytes for this cache?

$$ How many blocks does the cache have?

$$ How many bits in total $($including data bits, tag bits, and other metadata bits$)$ are

required for such a cache implementation?

$($b$)$ Repeat $($a$)$ with a $2-$way set associative write$-$back cache using LRU cache

replacement policy