Assume a processor has the following characteristics:

Base CPI $($No memory stalls$)=1\mathrm{.}5$

Processor Clock Rate $=2$GHz

Main memory access time $=100$ns

L$1$ Cache Miss Rate per instruction $=7\%$

L$2$ Cache $($direct mapped$)$ Hit Time $=12$ cycles

L$2$ Cache $($direct mapped$)$ Miss Rate $=3\mathrm{.}5\%$