Question: Assume base CPI = 1 without memory stalls; assume L 1 hit occurs within base CPI. L 1 access time = 1 cycle ( accounted

Assume base CPI=1 without memory stalls; assume L1 hit occurs within base CPI. L1 access time=1 cycle (accounted for within base CPI), L1 miss rate=10%. L2 access time=10 cycles, L2 miss rate=40%. L3 access time=50 cycles, L3 miss rate=80%, Main memory access time =100 cycles.
80% of instructions access L1 data cache.
Find the AMAT of P1
Find the overall CPI of P1

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