Given the following processor configuration of processor P$1($assuming $5$ cache levels to main memory$).$

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Assume base CPI$=1$ without memory stalls. Assume L$1$ hit occurs within base CPI.

L$1$ access time $=1$ cycle $($accounted for within base CPI$).$ L$1$ hit rate $=60\%.$

L$2$ access time $=10$ cycles. L$2$ miss rate $=20\%.$

L$3$ access time $=50$ cycles. L$3$ hit rate $=50\%.$

L$4$ access time $=200$ cycles. L$4$ miss rate $=60\%.$

The AMAT for the entire system is $30$ cycles.

Round the answer to the nearest integer. You can either round up or round down. For example, if you have the answer $1\mathrm{.}5,1$ or $2$ is acceptable.

DO NOT PUT ANY EXTRA SPACES in your answer.

Find the access time $($expressed in cycles$)$ for the main memory.

$70\%$ of instructions access the L$1$ data cache. Find the overall CPI of the given processor P$1.$