Assume that the following RISC$-$V code is executed on a pipelined processor with a $5-$stage pipeline with full forwarding and a $$always$-$taken$$ branch predictor. Draw the pipeline diagram and report number of clock cycles it takes to execute this sequence of instructions. Note: Result of branch is determined in EXE stage. Comments denote the true situation. # Taken LABELI: lw x$1,40($x$6)$ beq x$2,$ x$3,$ LABEL$2$ add xl$,$ x$6,$ x$4$ LABEL$2$: beq x$1,$ x$2,$ LABELI SW X$2,20($x$4)$ and xl$,$ xl$,$ x$4$ # Not Taken