Assume the following delays for components. Any component not listed is assumed to have a negligible delay.

Element Reg clk$-$to$-$q Reg setup MUX ALU MemRead MemWrite RegFile Read RegFile Setup BranchComp

Parameter

Delay $($ps$)3020502002502501502075$

Reg clk$-$to$-$q$/$setup applies to all registers in the datapath.

MemRead delay applies to both the IMEM and DMEM.

RegFile setup would be the setup time to consider when you're trying to write to the Reg File.

$1\mathrm{.}1$: What instruction type takes the longest to execute in this datapath $($i$.$e$.$ the instruction type that dictates the critical path of the datapath$)?$

$($a$)$

Load Instructions: lb$,$ lw$,...$

$($b$)$

Branches: beq, bne, $...$

$($c$)$

jal

$($d$)$

R$-$type ALU Instructions: add, xor, $...$

$($e$)$

lui

$($f$)$

auipc

$($g$)$

jalr

$($h$)$

Store Instructions: sw$,$ sbu, $...$

$($i$)$

I$-$type ALU Instructions: addi, xori, $...$

$100\%$

$1\mathrm{.}2$: For the instruction that takes longest to execute in this datapath, which components would be relevant to the critical path calculation? $($Do not include components that are still used by the instruction but are not on the critical path for the given delays$)$

$($a$)$

PC$-$MUX

$($b$)$

PC register

$($c$)$

IMEM

$($d$)$

Imm$-$Gen

$($e$)$

RegFile read

$($f$)$

Branch Comparator

$($g$)$

A$-$MUX

$($h$)$

B$-$MUX

$($i$)$

ALU

$($j$)$

DMEM

$($k$)$

WB$-$MUX

$($l$)$

RegFile Write

Select all possible options that apply.

$100\%$

$1\mathrm{.}3$: What is the critical path delay $($or the minimum operating clock period$)$ of this circuit, in ps$?$