Assume the following operation times for different MIPS datapath components:

Instruction memory: $500$ ps$,$ Data memory: $500$ ps$,$ ALU: $400$ ps$,$ Read or Write to Register File: $300$ ps Assume the following instruction mix: $30\%$ ALU, $40\%$ Loads, $20\%$ stores, $10\%$ branches.

The maximum frequency at which a Single Cycle design would run at is nearly

$590MHz$

$667MHz$

$500MHz$

$770MHz$

The maximum

$4\mathrm{.}0GHz$

$2\mathrm{.}0GHz$

$2\mathrm{.}5GHz$

$3\mathrm{.}3GHz$

The time it takes to complete the execution of a store operation in Multicycle design is about

$1700ps$

$1600ps$

$1500ps$

$2000ps$

The average CPI of the multi$-$cycle MIPS is about

$\backslash$table$[[4\mathrm{.}2],[3\mathrm{.}8],[4\mathrm{.}1],[4\mathrm{.}3]]$