Q1)

A 2-way 4-sets cache with LRU and block sequence access of B6, B4, B14, B2, B7, B3 will have the following blocks in Set#2

a. B7, B3

b. B6, B3

c. B2, B14

d. B6, B14

Q2)

Assume the following operation times for different MIPS datapath components:

Instruction memory: 400 ps, Data memory: 400 ps, ALU: 300 ps, Read or Write to Register File: 200 ps

Assume the following instruction mix: 30% ALU, 30% Loads, 20% stores, 20% branches.

The maximum frequency at which a Single Cycle design would run at is nearly

1500 MHz 1300 MHz 770 MHz 667 MHz

Q3)

The maximum frequency at which a Multicycle design would run at is nearly

5.0 GHz 1.3 GHz 3.3 GHz 2.5 GHz

Q4)

The average CPI of the multi-cycle MIPS is about

3.8 4.0 4.3 4.1