(b) Construct the Verilog code for the circuit in Figure Q1(b) by using the hierarchical method. Use module in Listing Q1(b) as the lower-level module. (12 marks) Shirt/Load Parallel output W Q D D Q Clock R3 R2 R1 RO Parallel input Figure Q1(b) module muxdff (D0, D1, Sel, Clock, Q); input DO, DI, Sel, Clock; output reg Q: always @(posedge Clock) if (!Sel) Q