$$

b) Place the instructions below at the forwarding clock cycle: Instruction Luv $13, 3($13) Addi St3, $t3, 10 Sub $to, $zero, $t3 Sw $10, 12($13) m Control Dead D A Memory adg2 RegRead Data B 2 H ALU (control) Forwarding Unit M Memory A (read data 1): D(Write data): E(Mux A): B (read data 2): E(RegWrite): C(sign extend input): G(Mux B): H(Mux 4 output): I(ALU output): K(Write Data): L(Mem write): N(Mux 3): P(Mux 3 output): M(Mem read): O(MEM/WB) write reg: MEMB (UXCE)