Description: Build and test the following circuits using gate-level modeling in Verilog HDL.

****PLEASE USE GATE-LEVEL MODELING AND NOTE THE REQUIREMENTS/DOCUMENTATION FOR EACH CIRCUIT****

1. 3-input minority function. Returns 1 if the number of 1s in the input is less than the number of 0s, otherwise returns 0.

2. Conditional 2-bit inverter. Takes three inputs x, y, and z and returns two outputs A and B. If x=0 then A=y and B=z, if x=1 then A=y' and B=z'. Don't use XOR gates for the implementation.

Requirements:

1. Create truth tables and use maps for simplification
2. Create a module for each circuit, instantiate it in a test module and test it.
3. For testing use all combinations of input values and show the corresponding output for all circuits

Documentation for each circuit:

1. Short text description.
2. Truth tables and maps
3. Gate level circuit diagram with components and wires labeled with the module and variable names used in the Verilog code.
4. Verilog source code (included as text, not image).
5. Verilog output showing the test results as explained in the requirements.