Description: Build and test the following circuits using gate-level modeling in Verilog HDL.

*****PLEASE USE GATE-LEVEL MODELING AND NOTE THE INSTRUCTIONS FOR EACH CIRCUIT BELOW*****

1. . 1-bit full adder by cascading two half adders. Create a separate module for the half adder.

2. 1-bit full adder direct implementation. Derive the output functions from the truth table and use 2-level NAND logic for the implementation.

3. 4-bit adder/subtractor with overflow detection by cascading four 1-bit full adders. Use multiple bit variables (vectors) for the inputs and output

Requirements:

1. Create truth tables and use maps for simplification (not needed for circuits 1 and 3 - just circuit 2)
2. Create a module for each circuit, instantiate it in a test module and test it.
3. The hierarchical circuits (1 and 3) should use instances of their constituent modules.
4. For testing use all combinations of input values and show the corresponding output for all circuits except for the 4-bit adder/subtractor (Circuit 3)
5. For testing the 4-bit adder/subtractor (Circuit 3) pick one positive and one negative number and add and subtract all combinations of them. Test also overflow situations for both add and subtract. Show the inputs/output both in binary and signed decimal.

Documentation for each circuit:

1. Short text description.
2. Truth tables and maps (Not needed for circuits 1 and 3 - just 2)
3. Gate level circuit diagram with components and wires labeled with the module and variable names used in the Verilog code. Use block diagrams for the components of the hierarchical circuits 1 and 3.
4. Verilog source code (included as text, not image).
5. Verilog output showing the test results as explained in the requirements.