by convention, a cache is named according to the amount of data it contains $,$ however, caches also require sram to store metadata such as tags and valid bits, for this exercise you will examine how a cache's configuration affects the toal amount of sram needed to implement it as well as the performance of the cache. for all parts, assume that the caches are byte addressable, the addresses are $64$ bits and words are $32$ bits. a$.$ calculate the total number of bits required to implement a $32$ kib cache with two word blocks. b$.$ calculate the total number of bits required to implement a $64$kib cache with a $32$ word blocks. c$.$ how much bigger is the $64$ kib cache $($implementation$)$ than the $32$ kib cache $($implementation$).$