Cache block size $($B$)$ can affect both miss rate and miss latency. Assuming a machine with a base CPI of $1,$ and an average of $1\mathrm{.}35$ references $($both instruction and data$)$ per instruction, find the block size that minimizes the total miss latency given the following miss rates for various block sizes.

$\backslash$table$[[8$:$4\%,16$:$3\%,32$:$2\%,64$:$1\mathrm{.}5\%,128$:$1\%$