Cache System Part A] Cache Design Assume a cache is 2-way set associative, has 16KB, 512-byte blocks and a physical address size of 22 bits Fill in the respective number of bits below Ta Set Block Offset Part BI Four-way Cache Memory Accesses The memory is byte addressable so that all memory accesses are to bytes. Physical addresses are 12 bits wide The cache is 4-way set associative with a 32-byte block size and 32 total cache blocks Set Block Offset ag Using the diagram of the cache table shown below, show where the following accesses will go in the cache Hit or Miss Access Binary Tag s 0: A21 LIU (o mostrecent, o i-second most rvceoL 0-third most recent. I l. least recently used Initial TAGs Comets in the cache Assame all cacbe ways are VALID ayb ay TAG LRETa IR ag L.R RTa SAMSUNG