A computer uses a byte-addressable virtual memory system with a two-entry TLB (translation look-aside buffer), a 2-way set associative cache, and a page table for a process P. Cache blocks are 8 bytes in size, while pages are 16 bytes in size. Assume, for the sake of this problem, that main memory contains only 4 frames and that the TLB and page table contents for Process P are as shown below:

What is the minimum number of bits required for a virtual address?

What is the minimum number of bits required for a physical address?

If the virtual address 0x38 is referenced, would a TLB hit occur?

To what physical address (if any) does virtual address 0x48 correspond? Does referencing virtual address 0x48 cause a TLB hit?