CLK PCWrite AdrSrc control MemWrite Unit RWrite ResultSrc 31:28 Cond ALUContro ALUSrcB ALUSrcA 2520 Funct 12 RdImmSrc Flags ALUFlags CLK CLK A1 A2 CLK CLK 19:16 WE3 WE RA1 RD1 RD nstr 15-1 ALUResult ALUOut EN EN 3.0 RA2 RD2 01 Instr /Data Memory 01 10 A3 Register WD3 File R15 15:12 4 10 WD CLK 23.0 Extend Extlmm Data Result Figure 7.30 Complete multicycle processor CLK PCWrite AdrSrc control MemWrite Unit RWrite ResultSrc 31:28 Cond ALUContro ALUSrcB ALUSrcA 2520 Funct 12 RdImmSrc Flags ALUFlags CLK CLK A1 A2 CLK CLK 19:16 WE3 WE RA1 RD1 RD nstr 15-1 ALUResult ALUOut EN EN 3.0 RA2 RD2 01 Instr /Data Memory 01 10 A3 Register WD3 File R15 15:12 4 10 WD CLK 23.0 Extend Extlmm Data Result Figure 7.30 Complete multicycle processor