Compare performance for single-cycle, multicycle, and pipelined datapaths vs calculating execution time for each using the gcc instruction mix

assume 2 ns for memory access, 2 ns for ALU operation, 1 ns for register read or write assume gcc instruction mix 23% loads, 13% stores, 19% branches, 2% jumps, 43% ALU

for pipelined execution assume 50% of the loads are followed immediately by an instruction that uses the result of the load 25% of branches are mispredicted branch delay on misprediction is 1 clock cycle jumps always incur 1 clock cycle delay so their average time is 2 clock cycles.