Complete a VHDL code for a one input and one output sequence detector to detect the sequence "1001" (overlaps are considered). The state diagram is given below, where the arrows indicate state transitions. State names and output values are given inside state circles. Use the partial code given below. library IEEE; use IEEE.STD LOGIC_I1164.ALL; entity state machine is Port (x:in STD_LOGIC; input z: out STD LOGIC;- output clk : in STD_LOGIC; reset in STD_LOGIC) end state machine