Complete the following VHDL code to implement a divider $(\frac{A}{B})$ using the repeated subtraction method. $[$ e$.$g$.$ if $A=14$ and $B=3,$ then the result can be calculated as: $14-3-3-3-3=2$

$$ The quotient $(Q)=$ number of subtractions $=4$ and the remainder $(R)=2]$

library IEEE;

use IEEE.std$\_$logic$\_1164.$all;

use IEEE.std$\_$logic$\_$unsigned.all;

entity divider is

port$($ CLK : in std$\_$logic;

A$,$ B : in std$\_$logic$\_$vector$(3$ downto $0)$;

Q$,R$ : out std$\_$logic$\_$vector$(3$ downto $0$