Complete the following VHDL code to implement a divider $($A$/$B$)$ using the repeated subtractionmethod. $($e$.$g$.$ if A$=14$ and B $=3,$ then the result can be calculated as: $14-3-3-3-3=2-$ The quotient $($Q$)=$ number of subtractions $=4$ and the remainder$($R$)=2]$library IEEE;use IEEE.std$\_$logic$\_1164.$all;use IEEE.std logic$\_$unsigned.all;entity divider isport $($CLKA$,$ B $,$ Q $,$ Rin std$\_$logic;: in std$\_$logic$\_$vector$(3$ downto $0)$; out std$\_$logic$\_$vector$(3$ downto $0))$;end divider;architecture behavioral of divider isYour design should include the following pins:$1.$ CLK: $($positive edge trigger input clock$)2.$ A: The first number $(4$ bits$)3.$ B: The Second number $(4$ bits$)4.$ Q: The quotient $(4$ bits$)5.$ R: The remainder $(4$ bits$)$Notes: Use behavioral description DO NOT use the following operators: $/,$ MOD, REM DO NOT use an algorithmic state machine. The calculation should be synchronous with the clock $($the result should be calculated in a single clock cycle at the rising edge of the input clock$)$ You have to use EDA Playground for this assignmentYou have to submit two files:$1.$ A VHDL code to implement your Design$\mathrm{.}2.$ A testbench file to simulate and test your design;a$.$Set the clock period to be $4$ns$.$b$.$ You have to cover all the possible cases for the input data $($except: B$="0000*$ and B$="1111")(224$ different cases$)$c$.$ For each case you have to:Select the value for A $($form $"0000"$ to $"1111")$ and the value for B $($from $"0001"$ to $"1110*),$Wait for two clock cycles