Complete the VHDL Code for a 32 bit ALU then create a "good" testbench to see it works:

--VHDL Code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ALU_32bit is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; s : in STD_LOGIC_VECTOR (3 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end ALU_32bit;

architecture Bhv_alu_32bit of ALU_32bit is component Arithmetic is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end component;

component Logic is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); i_b : in STD_LOGIC_VECTOR (31 downto 0); s : in STD_LOGIC_VECTOR (1 downto 0); result : out STD_LOGIC_VECTOR (32 downto 0)); end component;

component Shift is Port ( i_a : in STD_LOGIC_VECTOR (31 downto 0); c_in : in STD_LOGIC; s : in STD_LOGIC; result : out STD_LOGIC_VECTOR (32 downto 0)); end component; component mux33_4to1 is Port ( a,b,c,d:in STD_LOGIC_VECTOR(32 downto 0); s: in STD_LOGIC_VECTOR(1 downto 0); y: out STD_LOGIC_VECTOR(32 downto 0)); end component;

signal sg_arith :STD_LOGIC_VECTOR(32 downto 0); signal sg_logic :STD_LOGIC_VECTOR(32 downto 0); signal sg_shift :STD_LOGIC_VECTOR(32 downto 0);

begin p0:Arithmetic Port map(i_a,i_b,c_in,s(1 downto 0),sg_arith); p1:Logic Port map(i_a,i_b,s(1 downto 0),sg_logic); p2:Shift Port map(i_a,c_in,s(1),sg_shift); p3:mux33_4to1 Port map(sg_arith,sg_logic,sg_shift,"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ",s(3 downto 2),result);

end Bhv_alu_32bit;