Question: Computer architecture. Working VHDL code with Test cases please! I. 4-bit Binary Counter Design 1. Requirement Design a 4-bit binary counterwith asynchronous reset using behavioral

Computer architecture.

Working VHDL code with Test cases please!

Computer architecture. Working VHDL code with Test cases please! I. 4-bit Binary

I. 4-bit Binary Counter Design 1. Requirement Design a 4-bit binary counterwith asynchronous reset using behavioral implementation style. The component starts countingifCount Enable signal is 1, otherwise it will stop counting. The counter will reset to "0000" when Reset signal is 1. The carry out happens when the count value exceeds 15 (overflow occurs). The block diagram of this component is as Clock Count_Val(3:0) Count Enable 4-bits Counter Cout Reset below: The interface can be as below: entityCounterUnit_4Bits_Design is port( Count_Enable:instd_logic: Reset :instd_logic instd_logic: Cout:outstd_logic; Count_Val:outstd_logic_vector (3downto0) endShifterUnit_32Bits_Design

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