**Computer Organization and Architecture (Stallings 10th edition)

Consider a main memory system that consists of a number of memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signal. During the same 100ns, and for 500ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time.

a. What is the maximum number of stores that can be initiated in one second?

b. Sketch a graph of the maximum write rate (words per second as function of the module cycle time, assuming eight memory modules and a fixed bus busy time of 100ns.