Computer organization and design, mips instructions, please solve fast I will upvote for you

. Consider executing the following MIPS instruction: LW Sto, 4(50) Assume: Assume MIPS memory system with TLB and data cache Sso has the value: B49F_6A30 Assume MIPS 32-bit address, byte-addressable, with page size of 64K bytes. TLB has the following entries. Virtual Page Number (016-bit) Valid Dirty Physical Page Number (8-bit) F94B 0 45 B49F 0 C2 6A34 0 12 Data cache has the following features: o Size = 32768 bytes o 8-way association 6 Block size = 16 bytes . For the memory load address (of above instruction), compute the virtual address (in hex). 849F_6A30 B49F_6A34 B49F_6438 349F-6A3C