Consider a 16-byte cache with 2 bytes per block, a 2-way associative mapping and a LRU (least recently used) block replacement policy is used Assume the size of the main memory is 32 bytes. A MIPS program contains a sequence of read accesses to the main memory; the following table shows the corresponding read addresses. Complete the following table by filling a hit/miss (entry in the table shown below) of each access and the cache set number where the data is stored. (Assume the cache is empty initially) Cache set number decimal format Instruction No Address 0x00 0x04 0x01 0x05 0x08 0x02 0x18 0x11 0x14 0x00 0x1C 0x15 Hit Miss I2 I3 I4. I5 I6 I7 I8 I9 I10