Suppose we have a 32-bit MIPS processor, which includes a 2-way set associative data cache with capacity 16384 bytes, 16 bytes block, and a least recently used (LRU) replacement policy. Assume that the cache is empty (all valid bits are 0) before the following code is executed. 1 lw $t1,0x1040($0) 2 lw $t2,0x2044($0) 3 lw $t3,0x3048($0) 4 lw $t4,0x1044($0) 5 lw $t5,0x504c($0) 6 lw $t6,0x3040($0) For each of the six assembly instructions above, state i) the set field value for the accessed address, ii) the tag field value, and iii) if the instruction results in a cache hit or a cache miss.