Consider a byte addressable memory with 12 bit addresses. A cache is used with the following characteristics: cache size is 32 bytes block size is 4 bytes number of sets is 4 cache uses the LRU replacement policy Consider an array of integers accessed in the following order (where the array begins at address 0 times 100): arr [theta], arr [4], arr[8], arr[4], arr[theta] 1. The first access to arr[0] would be cold miss 2. The first access to arr[4] would be cold miss 3. The first access to arr[8] would be capacity miss 4. The second access to arr [4] would be hit 5. The second access to arr[o] would be conflict miss