Consider a pipelined implementation of a processor like MIPS, with 5 stages. These are: Instruction fetch,...

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Consider a pipelined implementation of a processor like MIPS, with 5 stages. These are: Instruction fetch, decode, execute, memory ops and writeback to registers. Assume that each stage takes 1 machine cycle. a) Show with a figure, the data hazard which will occur for the se- quence of instructions: addu $s0, $a0, $a2 addu $s1, $s0, Sto And how it can be solved either by a bubble insertion or by data forwarding. b) One way of implementing new instructions in a processor is to use an undefined instruction and in the handler (invoked due to this exception) carry out the function associated with the new instruc- tion. We want to implement an instruction which will replace registers $a0 and $al with their sum and difference. Describe the events which will take place when this instruction is fetched and decoded and the handler code to implement Consider a pipelined implementation of a processor like MIPS, with 5 stages. These are: Instruction fetch, decode, execute, memory ops and writeback to registers. Assume that each stage takes 1 machine cycle. a) Show with a figure, the data hazard which will occur for the se- quence of instructions: addu $s0, $a0, $a2 addu $s1, $s0, Sto And how it can be solved either by a bubble insertion or by data forwarding. b) One way of implementing new instructions in a processor is to use an undefined instruction and in the handler (invoked due to this exception) carry out the function associated with the new instruc- tion. We want to implement an instruction which will replace registers $a0 and $al with their sum and difference. Describe the events which will take place when this instruction is fetched and decoded and the handler code to implement