Consider an unpipelined processor. Assume it has $2-$ns clock cycle that it uses $4$ cycles for ALU operations and $5$ cycles for branches and $4$ cycles for memory operations. Assume that the relative frequencies of these operations are $60\%,25\%$ and $15\%,$ respectively. Suppose that due to clock skew and set up$,$ pipelining the processor adds $0\mathrm{.}2$ ns of overhead to the clock. Ignoring any latency impact, how much speed up in the execution rate will we gain from a pipeline?