Consider executing the following code on the $5-$stage pipelined datapath;

Which registers are read during the fifth clock cycle, and which registers are written at the end of the fifth clock cycle? Consider only the registers in the;

register file $($i$.$e$.,$ $$1,$ $$2,$ $$3,$ etc.$)$;

add $$1,$$$2,$$$3$

add $$4,$$$5,$$$6$

add $$7,$$$8,$$$9$

add $$10,$$$11,$$$12$

add $$13,$$$14,$$$15$