Consider the following assembly language code:

I$0$: lw $R$9,4,($$R$1)//$ LDW R$9=$ MEM$[$R$1+4]$;

I$1$: add $R$3,$$R$4,$$R$9//$ADD R$3=$ R$4+$ R$9$;

I$2$: lw $R$1,100($$R$3)//$LDW R$1=$ MEM$[$R$3+100]$;

I$3$: add $R$4,$$R$1,$$R$0//$ADD R$4=$ R$1+$ R$0$;

I$4$: lw $R$1,0($$R$3)//$LDW R$1=$ MEM$[$R$3+0]$;

I$5$: sub $R$3,$$R$1,$$R$4//$SUB R$3=$ R$1-$ R$4$;

I$6$: and $R$9,$$R$9,$$R$7//$AND R$9=$ R$9$ & R$7$;

I$7$: lw $R$2,100($$R$4)//$LDW R$2=$ MEM$[$R$4+100]$;

I$8$: sw $R$4,100($$R$2)//$STW MEM$[$R$2+100]=$ R$4$;

I$9$: add $R$1,$$R$5,$$R$4//$ADD R$1=$ R$5+$ R$4$;

Consider a pipeline with forwarding, hazard detection, and $1$ delay slot for branches. The pipeline is the typical $5-$stage IF$,$ ID$,$ E$,$ M$,$ WB MIPS design. For the above code, complete the pipeline diagram below $($instructions on the left, cycles on top$)$ for the code. Insert the characters IF$,$ ID$,$ E$,$ M$,$ WB for each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write$-$back stage writes to the register file. Label all data stalls $($Draw an X in the box$).$ Label all data forwards that the forwarding unit detects $($arrow between the stages handing off the data and the stages receiving the data$).$

a$)$ What is the final execution time of the code?

T$0$

T$1$

T$2$

T$3$

T$4$

T$5$

T$6$

T$7$

T$8$

T$9$

T$10$

T$11$

T$12$

T$13$

T$14$

T$15$

T$16$

T$17$

I$0$

I$1$

I$2$

I$3$

I$4$

I$5$

I$6$

I$7$

I$8$

I$9$

There is a total of $\_\_\_\_\_$ cycles

b$)$ Verify that the program takes number of cycles found in the previous part

c$)$ Assuming that the timings for the five pipeline stages are the ones given in the table below, find how long would it take to execute the code in part $($a$)$ and the respective speedups:

i$)$ Using a single$-$cycled processor.

ii$)$ Using a pipelined processor.

IF

ID

EX

MEM

WB

Pipeline Register

$45$ps

$50$ps

$35$ps

$65$ps

$30$ps

$15$ps