Consider the following assembly language code where there are $7$ instructions numbered I$0$ to I$6,$ consider a MIPS design:

I$0$:$$ ADD$$ R$4=$ R$1+$ R$0$;

I$1$:$$ SUB$$ R$9=$ R$3-$ R$4$;

I$2$:$$ ADD$$ R$4=$ R$5+$ R$6$;

I$3$:$$ LDW$$ R$2=$ MEM$[$R$3+100]$;

I$4$:$$ LDW$$ R$2=$ MEM$[$R$2+0]$;

I$5$:$$ STW$$ MEM$[$R$4+100]=$ R$2$;

I$6$:$$ AND$$ R$2=$ R$2$ &$$ R$1$;

$$ A$.$ Assuming no data forwarding, draw the time sequence pipeline diagram and calculate the number of clock cycles needed to complete the whole sequence of instruction.

$$B$.$ Assuming forwarding, draw the time sequence pipeline diagram and calculate the number of clocl cycles needed to complete the whole sequence of instruction.