Consider the following MIPS code that is being executed on the above 5-stage pipeline: Complete the following table showing the timing of the above code on the 5-stage pipeline MIPS processor (IF, ID, EX, MEM, WB). Draw an arrow showing forwarding between the stage that provides the data and the stage that receives the data Show all stall cycles by placing an X in the box to represent a stall cycle, 3 1: Iw 2. addi 3. or St1, 8(Sto) ?t2, St1,2 St3, St1, $t2 $t4, -4(St3) 5. sub 4 6 10 11 12 2 ID | EX | MEM | WB IF IF add ID EX WB or IF sub