Consider the following nonsense code:

LD R$3,80($R$4)$

DADDR$1,R4,R3$

SD $12($R$3),$ R$1$

$($a$)$ If this code is running on a variation $4$ MIPS with no data forwarding, how many clock cycles are

required $($from IF of first instruction to WB of last instruction$)?$ Be sure to show your work in the

form of a pipeline stage diagram, and explain the cause of each stall cycle.

$($b$)$ If this code is running on a variation $4$ MIPS with data forwarding, how many clock cycles are

required $($from IF of first instruction to WB of last instruction$)?$ Be sure to show your work in the

form of a pipeline stage diagram, and explain the cause of each stall cycle.